In pseudo line interlace, charge packets descriptive of picture elements (pixels) of an optical image are formed by integrating the charge carriers generated by photoconversion over only one field time. The charge packets are descriptive of pixels centered on odd scan line loci in any odd-numbered one of consecutively number field scans and are descriptive of pixels centered on even scan line loci in any even-numbered field. In any field each pixel has a dimension in the direction perpendicular to line scan (i.e. what is normally termed the "vertical" direction) equal to that of two television scan lines.
In true line interlace, on the other hand, charge packets are descriptive of pixels with a dimension in the direction perpendicular to line scan which dimension is equal to that of a single television scan line; and these charge packets are integrated over two fields (or one frame). Over a frame time, pseudo line interlace provides single-scan-line resolution for non-moving portions of the scanned image. The effective optical aperture is wider in the direction perpendicular to line scan when using pseudo line interlace than when using true line interlace. Accordingly, pseudo line interlace has a lower modulation transfer function (MTF) than true line interlace, but spatial aliasing in the direction perpendicular to line scan is somewhat better with pseudo line interlace.
C. H. Sequin in U.S. Pat. No. 3,801,884 issued Apr. 2, 1974 and entitled "CHARGE TRANSFER IMAGER DEVICES" describes a way of providing pseudo line interlace in a field-transfer type of imager wherein the gate electrodes in the image register are successively arranged in cycles having an even number of phases, greater than three. Sequin arranges image register pitch--that is, the extent of each cycle of gate electrodes receiving differently phased clocked voltages--to extend across a space corresponding to two adjacent lines of picture elements, or "pixels". During the integration time of odd fields, contiguous gate electrodes in a first half of the gate-electrode cycle are biased to induce potential barriers under them in each image register charge transfer channel, and the charge generated by photoconversion is collected under the contiguous gate electrodes in a second half of the gate-electrode cycle. During the integration time in even fields, the gate electrodes in the second half of the gate-electrode cycle are biased to induce potential barriers under them, and the charge is collected under gate electrodes in the first half of the gate-electrode cycle.
D. F. Battson in U.S. Pat. No. 4,507,684 issued Mar. 26, 1985 and entitled "REDUCING GRAIN IN MULTI-PHASE-CLOCKED CCD IMAGERS" teaches that "grain", a fixed pattern noise which is not attributable just to dark current variations and which persists even in relatively bright images, is caused by a form of partitioning noise attributable to the induced potential barrier exceeding a prescribed length (e.g., a few microns in the processing steps RCA Corporation uses to make CCD imagers). In clocking with at least four phases in the image register, the limitations of present-day photolithographic processes, which restrict minimum gate electrode length to a few microns, make the Sequin approach to pseudo line interlace an unfavorable one to take.
W. F. Kosonocky in U.S. Pat. No. 3,932,775 issued Jan. 13, 1976 and entitled "INTERLACED READOUT OF CHARGE STORED IN A CHARGE COUPLED IMAGE SENSING ARRAY" describes another way of providing pseudo line interlace between alternate fields in a field-transfer type of imager, when an image register with an even number of clock phases is used. During image integration times, potential energy barriers are erected under gate electrodes spaced half a gate electrode cycle apart. Dynamic clocking is resumed after image integration in different temporal phasings on alternate fields, when a two-phase-clocked image register is used. This combines pairs of successive charge packets of single-line-resolution photoresponse into charge packets of half-as-fine-resolution photoresponse, combining them in staggered spatial phasings in alternate fields thus to provide for pseudo line interlace.
An advantage of the Kosonocky scheme of providing pseudo line interlace is that the image register gate electrodes are biased the same way during image integration in each field. This avoids field rate flicker as may otherwise be caused by gate electrode length variations in charge-integrating well size from field to field. These variations may arise because gate electrodes have non-constant lengths or because the electromotive force potentials applied to the gate electrodes exhibit undesired variation between successive fields.
Apparatus is known in which errors in the CCD imager image samples that are of known characteristics can be compensated against, using offsets taken from a programmable read-only memory (PROM). Such apparatus, it is here pointed out, can be adapted to eliminate field rate flicker problems in imagers operated other than in accordance with the Kosonocky scheme of providing pseudo line interlace. Field rate flicker in the Sequin scheme of providing pseudo line interlace could be suppressed in this way, for example. Arrangements of this general type specifically for interline transfer CCD imagers are described by Hoffman in U.S. Pat. No. 4,200,934 issued Apr. 29, 1980 and entitled "CIRCUIT ARRANGEMENT FOR CORRECTING DIGITAL SIGNALS". Arrangements of this general type specifically for CCD imagers integrating image directly in the CCD charge transfer channels are described by P.A. Levine in U.S. patent application Ser. No. 779,861 filed Sept. 25, 1985, entitled "TEMPERATURE TRACKING DEFECT CORRECTOR FOR A SOLID STATE IMAGER", and assigned to RCA Corporation.
H. Elabd, W.F. Kosonocky, and D.F. Battson in U.S. patent application Ser. No. 685,725, filed Dec. 24, 1984, entitled "CCD IMAGERS WITH PIXELS AT LEAST THIRTY MICRONS LONG IN THE DIRECTION OF CHARGE TRANSFER", and assigned to RCA Corporation point out the desirability of clocking the image register of a CCD imagers in a large number of phases when pixel dimensions are long in the direction of charge transfer. This is done to avoid having to have overlong gate electrodes in the image register and thus keep grain acceptably low.
Kosonocky points out in U.S. Pat. No. 3,932,775 that his scheme of providing pseudo line interlace can also be carried out with an even number of clock phases larger than, two--e.g. four phases. However, this requires a special set of clocking signal voltages to be applied to the image register gate electrodes when changing from image integration to field transfer modes of operation. These special clocking signal voltages are needed to provide a proper transition between the gate electrode voltage condition during image integration and the gate electrode voltage clocking sequence during image transfer from the image register to the field storage register. That is, one cannot simply halt the dynamic clocking used during image transfer, perform image integration, then resume dynamic clocking during the next image transfer, as is done in two-phase clocking.
A shortcoming of the Sequin interlace scheme is that more than one gate electrode in the image register pitch is biased to induce a potential barrier thereunder during image integration. This can compromise imager low noise performance by raising dark current and its attendant shot noise slightly. During image integration it is common practice to reduce the depth of potential energy wells to lessen the amount of dark current integrated in them. Dark current generation increases at faster than linear rate with increase in well depth, so a short and deep well tends to accumulate more dark current charge than a long and shallow well of similar charge-containing capacity. While average dark current can be predicted and compensated against, the thermal noise associated with variations in dark current level, cannot be predicted and then compensated for. This effect would be noted in the Kosonocky imager also except for the fact that the .phi..sub.2-A, .phi..sub.4-A gate electrodes are usually made considerably shorter length than the .phi..sub.1-A, .phi..sub.3-A gate electrodes.
During image integration in a CCD imager, the image register of which is provided with anti-blooming drains, there can be some loss to the drains of photoresponse originating in those portions of the image register charge transfer channels in which potential barriers are induced. If only one gate electrode in the image register pitch is biased to induce a potential barrier thereunder, this loss is reduced, the present inventors point out. Not only does this improve overall photoefficiency by a small amount, it reduces a line-rate alias term in the imager response.